1. Field of the Invention
The invention relates to a printed wiring board and its production method. Further, the invention relates to a formation method of a resin layer on a metal layer, an inner conductor circuit treatment method, and a multilayer circuit board.
2. Description of the Related Art
Recently, electronic devices have been required to be compact, lightweight and high speed, and high densification of printed wiring boards has been advanced. Along with that, production of a printed wiring board by a semi-additive method using electroplating has been drawing an attention. As a semi-additive method, Japanese Patent Application Laid-Open No. 10-4254 discloses a method involving forming holds to be IVH in the resin surface in which a circuit is to be formed by laser; surface-roughening the resin surface with several μm by chemical roughening or plasma treatment; supplying a Pd catalyst; carrying out electroless plating in about 1 μm-thickness, forming a resist layer for pattern electroplating, carrying out wiring formation by pattern electroplating, and then removing the resist and a power supply layer existing in the portion other than the circuit and in such a manner the method makes more finer wiring formation possible as compared with a subtractive method with a high side etching degree. Japanese Patent Application Laid-Open No. 2003-158364 discloses a method of forming a circuit using a separable metal foil with a thickness of 5 μm or thinner formed on a supporting metal foil. The method makes production of a printed wiring board with a high reliability possible without requiring electroless plating of the surface of an insulating resin layer. However, according to these methods, the roughened shape inversely interferes the fine wiring formation. Moreover, the electric characteristics are deteriorated by the roughened shape. Japanese Patent Application Laid-Open (JP-A) No. 7-221444 discloses a method involving forming a copper layer with about 1 μm thickness on one face of a polyimide film by using an electron beam evaporation apparatus and layering the layer on an intermediate circuit by an adhesive or a prepreg to form an electric power supply layer. However, the substrate is very expensive and thus does not become popular.
After formation of the circuit in such a manner, gold plating on the outermost layer of the substrate is sometimes carried out. JP-A No. 7-221444 discloses a method of electrolytic gold plating to improve the connection reliability of terminals of a substrate and a semiconductor chip. As the gold plating method, there are an electroless gold plating method and an electrolytic gold plating method. Between them, the electroless gold plating method which requires no electric power supply is advantageous in high densification. However, in the case of gold plating after the circuit formation, a trouble that the gold plating is deposited on the resin sometimes occurs at the time of electroless gold plating according to the above-mentioned method disclosed in JP-A No. 10-4254. Especially, in the case the wiring pitches become 80 μm or narrower, the trouble occurs more frequently. Also, in the case of gold plating after the circuit formation, a trouble that the gold plating is deposited on the resin sometimes occurs owing to remaining of a copper foil on the resin at the time of electroless gold plating according to the above-mentioned method disclosed in JP-A No. 2003-158364.
Further, in recent years, to satisfy high densification of a substrate and speed up of signal transmission, built up type multilayer wiring boards have been used. JP-A No. 10-242638 discloses a method involving surface roughening a conductor circuit of a core substrate with a copper-nickel-phosphorus alloy, forming an insulating layer thereafter, and forming a conductor circuit on the insulating layer. JP-A No. 2000-282265 discloses a method of roughening in micron order the copper surface by using an aqueous solution containing an inorganic acid and a copper-oxidizing agent as main agents and at least one kind azole and etching suppressing agent as auxiliary agents. JP-A No. 9-246720 discloses a method involving forming continuous projected and recessed parts with height in a range of 1.5 to 5.0 μm by micro-etching and carrying out chromation and treatment with a coupling agent. As described, there are many methods for treating conductive circuits, and the methods can be divided broadly into methods of covering copper with an anti-rust treatment metal other than copper, methods of forming the roughened surface in micron order by roughening the conductor surface by etching or plating, and combination of these methods.
Along with the high densification of the substrate, the wiring has been made finer. Presently, it is highly required to form wiring with L/S=20/20 μm or lower by fine wiring formation techniques represented by the semi-additive method.
However, these methods tend to cause problems that the electric properties are deteriorated: that plating is deposited on the portion other than the conductor circuits along with the advanced fineness of the circuits: and that plating between fine circuits is insufficient. Further, there occur problems that the resistance of the conductor is increased because of etching of the conductor circuit and the dispersion of the wiring becomes wide.